The present invention relates to a memory system and related error detection and correction apparatus.
It is known that in current data processing systems semiconductor working memories are used having larger and larger capacity and higher and higher integration. Memory integrated circuits having 1M bit capacity have been available which enable the implementation of working memories having capacities ranging from 1M byte to several tens of M bytes, requiring the use of a limited number of integrated circuit components.
There exists a fundamental problem for such memories; namely, to assure the correctness of the data stored into and read out from memory. At this component integration level and with so large a memory capacity, it becomes very probable that some elementary storage cells of the memory system are or become temporarily defective. To overcome this defective condition, error detection and correction apparatuses are broadly used.
Basically, a corresponding code is stored in memory together with each stored information. Such code enables the correction of a single error and in some cases, to detect or correct double errors.
Such error correcting codes are generally referred to as SEC-DED codes, and require the storage into memory of an additional number of bits which is a function of the number of bits composing the information and the resolution capacity of the error code.
For a single byte of information comprising 8 bits, an error correcting code capable of correcting a single error and of detecting a double error requires the use of 5 additional bits. For 2 bytes of information, the SEC-DED code must comprise 6 bits and for 4 bytes of information the SEC-DED code must have 7 bits. Therefore, the higher the memory parallelism is, the lesser, percentage-wise, the memory capacity increment required to store the error codes.
Although perhaps not the sole reason, it is certainly a contributing factor to the design of memories having higher and higher parallelism, i.e., 16, 32 and 64 bits, which trades off against other factors.
A trade off consists of the fact that if it is desired to address and modify a single memory byte, each write operation of a single byte requires a complicated read operation of the whole word containing the byte and the writing of a new word containing the modified byte as well as the corresponding SEC-DEC code which must be constructed based on the whole word length.
Another trade off consists of the fact that the check operation and possible correction of the information read out from memory, requires a certain time which adds to the read operation time and which is greater the higher memory parallelism.
In practice, the checking and correcting portion of the information read out requires regeneration by means of a logical network generally comprising several stages of exclusive OR (EX-OR) circuits, a SEC-DEC code related to the information as read out from memory, and a comparison of such code with the corresponding SEC-DED code read out from memory. The comparison, performed in a comparing network, enables the generation of an error syndrome. An error correction logic receives as input the information read as well as the error syndrome, and provides as output the corrected information. Such an operation must be performed in time sequence and requires a predetermined time.
Today, EDAC integrated circuits are available on the market. An example is the integrated circuit AM 2960 manufactured by Advanced Micro Division (AMD), Sunnyvale, Calif. which performs the above mentioned function over a 16 bits parallelism and which may be interconnected to operate with any parallelism equal to or in multiples of 16 bits. Such components, which are very expensive, overcome the problem of the circuit complexity for the error correction circuits, but do not overcome the problem of the time spent for the check operation, which is in the range of 50-60 nsec., against a memory read cycle time in the order of 100-200 nsec. In addition, the above indicated check time of 50-60 nsec is the internal time required by the integrated circuit and can increase to more than 100 nsec when the delays are considered which are introduced by the interconnection and control circuits which connect the EDAC circuits with memory on one side and a system bus on the other side, thereby permitting communication between memory and the other units, such as a central processing unit.
A further reason for complication and delay is due to the fact that the corrected information which is output from the EDAC circuit, and transferred on the communication bus, is accompanied by a parity check bit for data integrity purpose. This control bit assures that the corrected information produced by the memory system is not affected by error in the transfer process on the communication bus up to the receiving unit, e.g., the central unit of the data processing system. Therefore the memory system is provided with a parity check bit generation network cascaded with the other circuit elements, which necessarily causes further delay in the effective availability of the information, or as a minimum, of the check bit, if a bypass is provided.
These disadvantages are overcome by the memory system and related error detection and correction apparatus which is the object of the present invention and where the memory is organized with a parallelism of multiple bytes, each byte being individually addressable and being provided with a related SEC-DED code.
Each byte read out, together with its related SEC-DED code, is used as address for a fast memory of reduced capacity, which implicitly, the same as a Pythagorean table performs a multiply operation; namely, performs the operations of SEC-DED code regeneration, comparison with the SEC-DED code read out from memory, generation of the error syndrome, correction of the possible error and generation of the parity check bit. All these operations are simultaneously performed in the time required to read the fast memory at byte level, and for a working memory having a parallelism multiple of one byte, as many "EDAC" fast memories are provided as are the bytes composing the word read out from memory.
In this way each byte may be handled, checked, corrected, independently from the others and all the procedural complexities and time-inefficiencies related to read-modify-write operations required for the writing of a single byte in a multiple byte parallelism working memory are avoided.
The same concept may be used to perform the information checking against the related parity check bit and the generation of the SEC-DED code to be written into memory. These operations may be performed by a small capacity, fast memory or by the same fast memory which is used as EDAC circuit. Read Only Memories as well as Read Write memories may be used for this purpose and therefore the developments offered by the technology in terms of speed and cost for both memory types may be fully exploited. The remarkable advantages which are achieved, fully justify the greater capacity required to the working memory, which, in case of 4 byte parallelism requires an overall parallelism of 32+20 bits against the 32+7 bits of a conventional memory system.